Three-Dimensional Interconnect Modeling for Nano-Scale VLSI Technologies

Designing high performance very large scale integration (VLSI) circuits has become more challenging than ever due to deep sub-micron effects and accelerating time-to-market cycles. With the increasing interconnect delay dominance and strong coupling effects, a small change in the design can cause new timing violations and result in design iterations. At the same time, the industry trend of integrating higher levels of circuit functionality on one chip and the widespread growth of wireless communication have triggered the proliferation of mixed analog-digital systems. The digital and the analog components share a common lossy substrate, which provides an alternative path for the current to reach difference devices and leads to more significant electro-magnetic couplings. Furthermore, the ever-increasing complexity of VLSI designs and integration circuit (IC) process technologies increases the mismatch between a circuit fabricated on the wafer and the one designed in the layout tool. Process induced variations can make the circuit performance deviate from the design specification and timing-convergence is getting harder and harder to achieve. Therefore, to perform fast circuit analysis and optimization, efficient extraction of compact yet accurate lumped circuit models of on-chip interconnect has become an extremely crucial